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Contact Us   3 months ago
Design Automation Manager - Intel Hillsboro, OR

This position is for a Design Automation Manager for the DA team in the Intel Custom Foundry Group. Intel Custom Foundry Group is Intel's exciting new venture into collaborating with Industry hardware leaders and bringing their products onto Intel's leading edge process technology. The DA team within Intel Custom Foundry Design Team is looking for talented individuals who wish to be a pa

Contact Us   4 months ago
Design Automation Lead Engineer - Intel Hillsboro, OR

The successful candidate must possess a minimum of Bachelor of Science(MS preferred) in Computer/Electrical Engineering with a minimum 6 yrs of relevant industry experience. Additional qualifications include:Good understanding of the full design flow for an Analog design.Proficient with SKILL, TCL, PERL and shell scriptingGood understanding of digital design, circuits, layoutThorough understanding

Contact Us   4 months ago
Acceleration IP DFX Design Engineer - Intel Phoenix, AZ

“This job requisition is to facilitate an intern conversion”Job Description: As the QAT IP DFX design engineer within the Silicon Engineering group of DCG/Network Platform Group, you will play a key role in the development of acceleration IPs for Intel Quick Assist Technology. As a member of the QAT design team, you will work with the IP/SoC Architecture team

Contact Us   4 months ago
Acceleration IP RTL Design Engineer - Intel Phoenix, AZ

“This job requisition is to facilitate an intern conversion”As the QAT IP RTL design engineer within the Silicon Engineering group of DCG/Network Platform Group, you will play a key role in the development of acceleration IPs for Intel Quick Assist Technology. As a member of the QAT design team, you will work with the IP/SoC Architecture team to define the IP micro-architecture, deve

Contact Us   10 months ago
Graduate Technical Intern - Intel Folsom, California

Responsibilities: Implement logic from micro-architectural specifications - Interact with Architects closely, help define the specs, boundary conditions & close any logic definition gaps- Design FSMs, logic & DFT features interfacing with Analog blocks- Code RTL assertions & MCP (multi-cycle path) checks in critical logic areas- Debug Pre-si Logic issues, bugs & implement robus

Contact Us   1 year ago
Supervisor Plant Facilties - des moines, iowa

CenturyLink (NYSE: CTL) is a global communications, hosting, cloud and IT services company enabling millions of customers to transform their businesses and their lives through innovative technology solutions. CenturyLink offers network and data systems management, Big Data analytics and IT consulting, and operates more than 55 data centers in North America, Europe and Asia. The company provides br

Contact Us   1 year ago
CONSTRUCTION PROJECT ADMINISTRATOR - greeley, colorado

CenturyLink (NYSE: CTL) is a global communications, hosting, cloud and IT services company enabling millions of customers to transform their businesses and their lives through innovative technology solutions. CenturyLink offers network and data systems management, Big Data analytics and IT consulting, and operates more than 55 data centers in North America, Europe and Asia. The company provides br

$5.00   1 year ago
ASIC Physical Designers - Austin

ASIC Physical Designers Our client, a multinational semi-conductor Fortune 500 company is seeking a ASIC Physical Designers ' located in Austin, TX for a contract job opportunity. Qualified and interested candidates please apply now using the submit button! All candidates must be US Citizens or Green card Holders Kelly Services(R) has been providing outstanding employment opportunities to the

Contact Us   1 year ago
Physical Design Engineer - Intel Phoenix, Arizona

Responsibilities include, but are not limited to: - Extensive knowledge & hands-on experience on full chip top-level integration including analog macros. - Block-level floor planning - Logic synthesis of design blocks, timing constraints development. - Formal Equivalence Verification (FEV) using Cadence LEC tool. - Auto Place-and-Route (APR) using Synopsys ICC tools - Timing verification usin


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Last Updated on: April 27, 2017
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